First Google and now Facebook use our Concurrent JIT Compilation Scheme

At PLDI’11 we have demonstrated that a concurrent dynamic compilation model works really well in our paper “Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator”. This work has also been presented at Euro LLVM’12 under the title “Reducing dynamic compilation latency - concurrent and parallel dynamic compilation”. Three years later Google announces support for concurrent compilation to make Chrome, more specifically the V8 JavaScript engine, faster. More recently, Facebook announced concurrent JIT compilation support in HHVM, their open source virtual machine designed for executing programs written in Hack and PHP. Neither Google nor Facebook give our research any credit

nSIM - Turning research into a product

Very happy to see our simulation research made it into a very successful Synopsys Inc. product making customers happy.

Research Impact of Pasta Project

The official case study about the research impact of The EnCore Microprocessor and the ArcSim Simulator project has been released. We are all very happy to see industry value our ideas and work.

Presenting at Euro LLVM'12 Conference

I received an invitation to present the outcome of my PhD at the Euro LLVM’12 conference. It seems that at that time we were the first ones to have built a production ready concurrent JIT compiler using the LLVM framework. A few years later Google and Facebook apply our research results in their virtual machines.

Reducing dynamic compilation latency - concurrent and parallel dynamic compilation

The main challenge faced by a dynamic compilation system is to detect and translate frequently executed program regions into highly efficient native code as fast as possible. Depending on application requirements, state-of-the-art dynamic-compilation …

Flexible Ultra-High Speed Instruction Set Simulation - ArcSim

ArcSim is our 'Swiss army knife' for high-speed functional and cycle accurate instruction set simulation of the EnCore processor. It provides various simulation modes and yields a wealth of statistics and metrics about simulated programs.

Encore Castle Fully Functional

The second silicon implementation of an extended EnCore processor is a test-chip codenamed Castle, fabricated in a generic 90nm CMOS process. All of the EnCore test chips are named after hills in Edinburgh; Castle is named after the rock on which Edinburgh Castle is built.

Processor Automated Synthesis by iTerative Analysis - PASTA

In the PASTA project we seek to automate the design and optimisation of customisable embedded processors. We do this by creating tools that are able to learn about the physical characteristics of the underlying silicon technology, and use that knowledge to synthesise the structure of an embedded processor.