At PLDI’11 we have demonstrated that a concurrent dynamic compilation model works really well in our paper “Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator”. This work has also been presented at Euro LLVM’12 under the title “Reducing dynamic compilation latency - concurrent and parallel dynamic compilation”.
More recently, Facebook announced concurrent JIT compilation support in HHVM, their open source virtual machine designed for executing programs written in Hack and PHP.
Neither Google nor Facebook give our research any credit
[Article in Japanese]
Instruction set simulators (ISS) are vital tools for compiler, operating system, and application development as well as processor architecture design space exploration and verification. Because the demands are so different, designing an ISS that caters to all of the above application scenarios is a constant challenge. On the one hand HW verification demands absolute precision with respect to architectural behavior. Even for corner case randomly generated scenarios that are unlikely to occur in reality. Compiler developers on the other hand require functional correctness, performance, and rich profiling feedback to create an optimizing compiler before the actual HW is ready.
The DesignWare® ARC® nSIM Instruction Set Simulator provides an instruction accurate processor model for the DesignWare ARC processor families.
Very happy to see our simulation research made it into a very successful Synopsys Inc. product making customers happy.
The official case study about the research impact of The EnCore Microprocessor and the ArcSim Simulator project has been released. We are all very happy to see industry value our ideas and work.