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Speeding up dynamic compilation: concurrent and parallel dynamic compilation,- PhD Thesis
Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation,- Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES’12), May 2012.
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation,- Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (IC-SAMOS’11), Samos, Greece, July 19-22, 2011.
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator,- Proceedings of the ACM SIGPLAN 2011 Conference on Programming Language Design and Implementation (PLDI’11), June 2011.
Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator,- Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (IC-SAMOS’10), Samos, Greece, July 19-22, 2010.
Integrated Instruction Selection and Register Allocation for Compact Code Generation Exploiting Freeform Mixing of 16- and 32-bit Instructions,- Proceedings of the 8th annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO’10), Toronto, Canada, April 2010.