During my PhD at The University of Edinburgh I was a member of the PASTA project. In the PASTA project we seeked to automate the design and optimisation of customisable embedded processors. We did this by creating tools that were able to learn about the physical characteristics of the underlying silicon technology, and use that knowledge to synthesise the structure of an embedded processor.
As the processor was a flexible entity without a pre-defined instruction set, the compiler and instruction set simulator for that processor must be automatically extended or generated. Furthermore, the code optimisations that the compiler performs when translating from source code to the synthetic architecture, must also be synthesised.
The four main areas for automated synthesis were:
- The processor architecture,
- the micro-architecture,
- the instruction set simulator, and
- the compiler.
However, the information on which to make automated decisions in each case was different. At the micro-architecture level we need to know how each micro-architecture option translates into speed, energy and die area. At the architectural level we need to know how each instruction set option translates into clock cycles of execution time, and at the compiler level we need to know how each optimisation reduces the overall number of instructions executed, and maximises the effectiveness of the memory system.
The challenge of our research is that all three areas are inter-dependent, and ultimately depend on the characteristics of the silicon on which the system is based. By blurring the boundary between hardware and software, and by automating the process of adjusting that boundary, we hope to create a system that can perform design trade-offs in seconds when currently it takes an experienced designer several days.
The PASTA project began in September 2006, funded by a research grant from EPSRC. I have joined the PASTA team in 2008.
The field of research during my PhD was in the area of speeding up Instruction Set Simulation by using concurrent and parallel dynamic compilation. The instruction set simulator ArcSim served as the basis for implementing research ideas.
ArcSim was our ‘Swiss army knife’ for high-speed functional and cycle accurate instruction set simulation of the EnCore processor. It provides various simulation modes and yields a wealth of statistics and metrics about simulated programs.
Back in my PhD days I created a demo to showcase the benefit of a concurrent and parallel JIT. It shows the simulation of a bare metal application that embeds a WebM encoded video together with all the logic to decode and render the video to a virtual screen. The demo shows the same application running in three different simulation modes (interpretive mode, singe JIT thread, multiple JIT threads). The key observation is that by using multiple concurrent JIT threads native code is available sooner:
To find out more about my research please check out my PhD Thesis titled Speeding up dynamic compilation: concurrent and parallel dynamic compilation.