At PLDI’11 we have demonstrated that a concurrent dynamic compilation model works really well in our paper “Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator”. This work has also been presented at Euro LLVM’12 under the title “Reducing dynamic compilation latency - concurrent and parallel dynamic compilation”.
Instruction set simulators (ISS) are vital tools for compiler, operating system, and application development as well as processor architecture design space exploration and verification. Because the demands are so different, designing an ISS that caters to all of the above application scenarios is a constant challenge. On the one hand HW verification demands absolute precision with respect to architectural behavior. Even for corner case randomly generated scenarios that are unlikely to occur in reality. Compiler developers on the other hand require functional correctness, performance, and rich profiling feedback to create an optimizing compiler before the actual HW is ready.
Very happy to see our simulation research made it into a very successful Synopsys Inc. product making customers happy.
The official case study about the research impact of The EnCore Microprocessor and the ArcSim Simulator project has been released. We are all very happy to see industry value our ideas and work.
I received an invitation to present the outcome of my PhD at the Euro LLVM’12 conference. It seems that at that time we were the first ones to have built a production ready concurrent JIT compiler using the LLVM framework.
A few years later Google and Facebook apply our research results in their virtual machines.
The second silicon implementation of an extended EnCore processor is a test-chip codenamed Castle, fabricated in a generic 90nm CMOS process. All of the EnCore test chips are named after hills in Edinburgh; Castle is named after the rock on which Edinburgh Castle is built.