Projects

ARC Processor Models - nSIM

The DesignWare® ARC® nSIM Instruction Set Simulator provides an instruction accurate processor model for the DesignWare ARC processor families.

Flexible Ultra-High Speed Instruction Set Simulation - ArcSim

ArcSim is our ‘Swiss army knife’ for high-speed functional and cycle accurate instruction set simulation of the EnCore processor. It provides various simulation modes and yields a wealth of statistics and metrics about simulated programs.

Processor Automated Synthesis by iTerative Analysis - PASTA

In the PASTA project we seek to automate the design and optimisation of customisable embedded processors. We do this by creating tools that are able to learn about the physical characteristics of the underlying silicon technology, and use that knowledge to synthesise the structure of an embedded processor.

Haskell Bottom Up Rewrite Generator - HBURG

Design and implementation of a code generator generator based upon Tree Pattern Matching and Dynamic Programming using the functional programming language Haskell.

UI for the BSD ports system - PortBrowser

The PortBrowser is a FREE, easy to use implementation of a front end written for the BSD ports system. It has been developed for OpenBSD but it should also work on FreeBSD.

Publications

The main challenge faced by a dynamic compilation system is to detect and translate frequently executed program regions into highly …

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through …

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through …

Abstract Dynamic Binary Translation (DBT) is the key technology behind cross-platform virtualization and allows software compiled for …

Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. …

For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to …

Building compiler back ends from declarative specifications that map tree structured intermediate representations onto target machine …

Talks

Past & Upcoming

In this talk we want to present two innovative contributions that work together to effectively reduce dynamic compilation latency. The …

Posts

At PLDI’11 we have demonstrated that a concurrent dynamic compilation model works really well in our paper “Generalized …

Instruction set simulators (ISS) are vital tools for compiler, operating system, and application development …

Very happy to see our simulation research made it into a very successful Synopsys Inc. product making customers happy.

The official case study about the research impact of The EnCore Microprocessor and the ArcSim Simulator project has been released. We …

I received an invitation to present the outcome of my PhD at the Euro LLVM’12 conference. It seems that at that time we were the …

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