I received an invitation to present the outcome of my PhD at the Euro LLVM’12 conference. It seems that at that time we were the first ones to have built a production ready concurrent JIT compiler using the LLVM framework.
ArcSim is our ‘Swiss army knife’ for high-speed functional and cycle accurate instruction set simulation of the EnCore processor. It provides various simulation modes and yields a wealth of statistics and metrics about simulated programs.
The second silicon implementation of an extended EnCore processor is a test-chip codenamed Castle, fabricated in a generic 90nm CMOS process. All of the EnCore test chips are named after hills in Edinburgh; Castle is named after the rock on which Edinburgh Castle is built.
In the PASTA project we seek to automate the design and optimisation of customisable embedded processors. We do this by creating tools that are able to learn about the physical characteristics of the underlying silicon technology, and use that knowledge to synthesise the structure of an embedded processor.